Location: Faculty lounge, elevator C, floor 2, Electrum, Kista

Tsunenobu Kimoto (Kyoto University)

Abstract:
SiC has attracted increasing attention as a wide bandgap semiconductor suitable for advanced power devices. In this seminar, progress in 1 kV-class SiC trench MOSFETs and characterization of the MOS interface are presented. 3 kV reverse-blocking SiC MOSFETs toward a bidirectional switch are also demonstrated. In the second part, reduction of basal plane dislocations (BPDs), which act as a nucleation site of a single Shockley stacking fault, in a SiC epitaxial layer is described. Combining the BPD reduction and introducing a recombination-enhancing layer, elimination of bipolar degradation has been achieved.

Bio:
Tsunenobu Kimoto received the M.E. degrees in Electrical Engineering from Kyoto University, Japan, in 1988, and he joined Sumitomo Electric Industries, LTD. In 1990, he started his academic career at Kyoto University, and received the Ph.D. degree in 1996, based on his study on SiC. From September in 1996 through August in 1997, he was a visiting scientist at Linkoping University, Sweden. He is currently a Professor at Department of Electronic Science and Engineering, Kyoto University. He is a member of IEEE (Fellow), MRS, JSAP (Fellow),  IEICE, and IEE. He is also a board director of JSAP.